Job Title: Synthesis/DFT Engineer

Department: R&D Department

Working place: Changsha, Shanghai

Responsibilities:

1. Responsible for chip-level DFT design and integration, including SCAN, MBIST and JTAG;

2. Responsible for automatic generation and simulation of DFT test vectors;

3. Working closely with design engineers to improve DFT test coverage;

4. Working closely with product engineers and test engineers to debug and resolve DFT test vectors that fail on the test machine;

5. Responsible for chip-level synthesis.

Qualifications:

1. Bachelor degree or above in computer science, microelectronics or other related majors;

2. More than 5 years relevant work experience.