Job Title: SoC Low Power Design Engineer

Department: R&D Department

Work Location: Changsha, Shanghai

Responsibilities:

1. Participating in the overall architecture design of the chip;

2. Responsible for the definition and analysis of power consumption scenarios;

3. Formulating the power consumption design scheme of the chip, including Clock Domain, Power Domain, Power Sequence, Power Supply, low power scheme, Reset scheme and Thermal scheme;

4. Responsible for the simulation environment, simulation verification and result analysis of key power consumption scenarios.

Qualifications:

1. Master's degree or above in a related major, over 5 years’ working experience in IC industry, specified in design and mass production of large chips;

2. Familiar with computer architecture, ARM or RISC-V architecture;

3. Proficient in applying various tools of power analysis, and able to formulate power workflow.